DPU QDMA Subsystem for PCIe/Ethernet

FPGA development kit available now:

• Ideal to replace Xilinx^® LogiCORE ™ QDMA for PCI Express^® (PCIe)
• DPDK driver support
• Virtual I/O Device (VIRTIO) Version 1.1
• PCIe to Ethernet FPGA design 
• Ethernet:  100 Gigabit 
• PCIe : Gen3 x16 
• FPGA: Xilinx 
• Support user-define descriptor format
• Support user-define packet payload size to optimize for performance optimization
• Support for both the AXI4-Memory Mapped and AXI4-Stream interfaces per queue
• Multi-queue sets host to controller/ controller to host descriptor rings
• Supports Polling Mode (Status Descriptor Write Back)
• Controller to host stream interrupt moderation
• 2K MSI-X vectors
• Performance: 90Gbps+ PCIe-Ethernet transfer with Xilinx FPGA 
• Demo available using poll mode driver and a Network Interface Card (NIC) bind to the poll mode driver
• Demo: Bypassing the kernel using user space